In recent years, to reduce a size of a display device and to reduce cost, there is being progressed development of a display device in which both a display unit including a pixel circuit and a gate driver for driving a gate bus line (scanning signal line) are formed on the same substrate. FIG. 27 is a block diagram showing an example of a configuration of a gate driver of such a conventional display device. In addition, FIG. 28 is a circuit diagram showing an example of a configuration of one stage of a shift register that constitutes the gate driver.
As shown in FIG. 27, the gate driver includes a shift register 90 of plural stages (the same number of stages as that of gate bus lines). Each stage of the shift register 90 is a bistable circuit that is in either one of two states (a first state and a second state) at each time point, and outputs a signal indicating this state, as a scanning signal. In this way, the shift register 90 includes plural bistable circuits SR. Each bistable circuit SR is provided with input terminals for receiving two-phase clock signals CKA (hereinafter, referred to as a “first clock”) and CKB (hereinafter, referred to as a “second clock”) respectively, an input terminal for receiving a low-level power source voltage VSS, an input terminal for receiving a set signal SET, an input terminal for receiving a reset signal RESET, and an output terminal for outputting a scanning signal GOUT. The scanning signal GOUT outputted from each stage (bistable circuit) is provided to a next stage as a set signal, and is also provided to a pre-stage as a reset signal.
As shown in FIG. 28, the bistable circuit includes four thin-film transistors T91, T92, T93, and T94, and a capacitor C9. The bistable circuit also includes four input terminals 91 to 94 and an output terminal 95, in addition to the input terminal for the low-level power source voltage VSS. A source terminal of the thin-film transistor T91, a drain terminal of the thin-film transistor T92, and a gate terminal of the thin-film transistor T93 are connected to each other. Note that a region (wiring) in which these terminals are connected to each other is called a “netA” for convenience.
In the thin-film transistor T91, a gate terminal and a drain terminal are connected to the input terminal 91 (that is, in a diode connection), and the source terminal is connected to the netA. In the thin-film transistor T92, a gate terminal is connected to the input terminal 92, the drain terminal is connected to the netA, and a source terminal is connected to the power source voltage VSS. In the thin-film transistor T93, the gate terminal is connected to the netA, a drain terminal is connected to the input terminal 93, and a source terminal is connected to the output terminal 95. In the thin-film transistor T94, a gate terminal is connected to the input terminal 94, a drain terminal is connected to the output terminal 95, and a source terminal is connected to the power source voltage VSS. In the capacitor C9, one end is connected to the netA, and the other end is connected to the output terminal 95.
In the configuration as described above, each stage (bistable circuit) of the shift register 90 operates as follows ideally. Note that FIG. 29 is a timing chart for describing the operation of each stage of the shift register 90. The first clock CKA that becomes at a high level at every other horizontal scanning period is provided to the input terminal 93. The second clock CKB of which a phase is shifted by 180 degrees from a phase of the first clock CKA is provided to the input terminal 94. During a period before a time point t0, a potential of the netA and a potential of the scanning signal GOUT (a potential of the output terminal 95) are at a low level.
When reaching the time point t0, a pulse of the set signal SET is provided to the input terminal 91. Because the thin-film transistor T91 is in a diode connection as shown in FIG. 28, the thin-film transistor T91 becomes in an on state by the pulse of this set signal SET, and the capacitor C9 is charged. As a result, the potential of the netA changes from the low level to a high level, and the thin-film transistor T93 becomes in an on state. In this case, the first clock CKA is at a low level during a period from the time point t0 to the time point t1. Therefore, during this period, the scanning signal GOUT is maintained at the low level. Also, during this period, since the reset signal RESET is at a low level, the thin-film transistor T92 is maintained in an off state. Therefore, the potential of the netA does not decrease during this period.
When reaching the time point t1, the first clock CKA changes from the low level to the high level. In this case, because the thin-film transistor T93 is in an on state, a potential of the input terminal 93 increases and the potential of the output terminal 95 also increases. Here, as shown in FIG. 28, because the capacitor C9 is provided between the netA and the output terminal 95, the potential of the netA also increases (the netA is bootstrapped) with the increase in the potential of the output terminal 95. As a result, a large voltage is applied to the thin-film transistor T93, and the potential of the scanning signal GOUT increases to a high-level potential of the first clock CKA. Consequently, a gate bus line connected to the output terminal 95 of the bistable circuit becomes in a selected state. Note that, during a period from the time point t1 to a time point t2, the second clock CKB is at a low level. Therefore, because the thin-film transistor T94 is maintained in an off state, the potential of the scanning signal GOUT does not decrease during this period.
When reaching the time point t2, the first clock CKA changes from the high level to the low level. Accordingly, the potential of the output terminal 95 decreases with the decrease in the potential of the input terminal 93, and the potential of the netA also decreases via the capacitor C9. Moreover, at the time point t2, a pulse of the reset signal RESET is provided to the input terminal 92. Accordingly, the thin-film transistor T92 becomes in an on state. As a result, the potential of the netA changes from the high level to the low level. Moreover, at the time point t2, the second clock CKB changes from the low level to a high level. Accordingly, the thin-film transistor T94 becomes in an on state. As a result, the potential of the output terminal 95, that is, the potential of the scanning signal GOUT, becomes at the low level.
As described above, the scanning signal GOUT outputted from each stage (bistable circuit) is provided to the next stage as the set signal SET, as shown in FIG. 27. In this manner, the plural gate bus lines provided in the display device sequentially become in the selected state in each horizontal scanning period, and writing is performed to a pixel capacitance within the pixel circuit for each row.
Regarding a present invention, the following prior-art document is known. Japanese Unexamined Patent Application Publication No. 2005-50502 describes a shift register which is configured such that a scanning signal that is outputted from a (k+1)-th stage bistable circuit is used as a reset signal of a k-th stage bistable circuit.